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Message
From: OpenCores CVS Agent<cvs@w...>
Date: Fri May 21 13:47:50 CEST 2004
Subject: [cvs-checkins] uart16550/rtl/verilog uart_receiver.v
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: tadejm 04/05/21 13:47:50
Modified files:
rtl/verilog : uart_receiver.v
Log message:
Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs.
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