|
Message
From: OpenCores CVS Agent<cvs@w...>
Date: Fri May 21 13:44:42 CEST 2004
Subject: [cvs-checkins] uart16550/rtl/verilog uart_regs.v
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: tadejm 04/05/21 13:44:42
Modified files:
rtl/verilog : uart_regs.v
Log message:
Added synchronizer flops for RX input.
|
 |
Browse
