LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: OpenCores CVS Agent<cvs@w...>
    Date: Fri May 14 18:20:26 CEST 2004
    Subject: [cvs-checkins] usb11/bench/verilog usb_defines.v
    Top
    CVSROOT: /cvsroot/alfoltran
    Module name: usb11
    Changes by: alfoltran 04/05/14 18:20:23

    Added files:
    bench/verilog : usb_defines.v

    Log message:
    Verilog defines file for testbench.

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.