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From: OpenCores CVS Agent<cvs@w...>
Date: Sat Feb 28 17:01:53 CET 2004
Subject: [cvs-checkins] simple_spi/ ench/verilog/spi_slave_model.v enc ...
CVSROOT: /cvsroot/rherveille
Module name: simple_spi
Changes by: rherveille 04/02/28 17:01:52

Added files:
bench/verilog : spi_slave_model.v tst_bench_top.v
wb_master_model.v
sim/rtl_sim/bin: Makefile
sim/rtl_sim/run: Makefile ncsim.log ncvlog.log simvision.sv
stdout.log
sim/rtl_sim/run/ncwork: cds.lib hdl.var
sim/rtl_sim/run/ncwork/work: .cdsvmod .inca.db.135.linux
.inca.db.148.lnx86
inca.linux.135.pak
inca.lnx86.148.pak
sim/rtl_sim/run/waves: waves.do

Log message:
Initial testbench release added