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Message
From: OpenCores CVS Agent<cvs@w...>
Date: Fri Dec 19 12:11:33 CET 2003
Subject: [cvs-checkins] pci/ pps/test/rtl/verilog/pci_bridge32.v pps/t ...
CVSROOT: /home/oc/cvs
Module name: pci
Changes by: mihad 03/12/19 12:11:32
Modified files:
apps/test/rtl/verilog: pci_bridge32.v pci_test_top_2clks.v
pci_user_constants.v test.v
apps/test/syn/synplify: pci_test_top.prj pci_test_top.ucf
pci_test_top_2clks.sdc
bench/verilog : pci_behaviorial_master.v
pci_bench_common_tasks.v
pci_regression_constants.v
pci_testbench_defines.v system.v
doc : pci_specification.doc pci_specification.pdf
rtl/verilog : pci_bridge32.v pci_conf_space.v pci_constants.v
pci_in_reg.v pci_io_mux.v pci_master32_sm_if.v
pci_rst_int.v pci_target32_interface.v
pci_target32_sm.v pci_target_unit.v
pci_user_constants.v pci_wb_slave.v
pci_wbs_wbb3_2_wbb2.v pci_wbw_wbr_fifos.v
sim/rtl_sim/bin: hdl.var
sim/rtl_sim/log: get_log_err_war
sim/rtl_sim/run: ncelab.args run_pci_sim_regr.scr top_groups.do
Log message:
Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.
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