LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: OpenCores CVS Agent<cvs@w...>
    Date: Mon Dec 15 13:25:31 CET 2003
    Subject: [cvs-checkins] pci/ im/rtl_sim/bin/rtl_file_list.lst im/rtl_s ...
    Top
    CVSROOT: /home/oc/cvs
    Module name: pci
    Changes by: mihad 03/12/15 13:25:26

    Modified files:
    sim/rtl_sim/bin: rtl_file_list.lst sim_file_list.lst
    Added files:
    bench/verilog : top.v
    Removed files:
    rtl/verilog : top.v meta_flop.v

    Log message:
    Moved top.v to bench directory. Removed unneeded meta_flop,
    modified files list files accordingly.

     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.