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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Tue, 23 Sep 2003 15:09:27 +0200
Subject: [cvs-checkins] vga_lcd/ ench/verilog/sync_check.v ench/verilo ...
CVSROOT: /home/oc/cvs
Module name: vga_lcd
Changes by: markom 03/09/23 15:09:26
Modified files:
bench/verilog : sync_check.v test_bench_top.v tests.v
wb_mast_model.v
sim/rtl_sim/bin: Makefile
Log message:
all WB outputs are registered, but just when we dont use cursors
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