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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 9 Jul 2003 13:53:50 -0100
Subject: [cvs-checkins] ethernet/rtl/verilog xilinx_dist_ram_16x32.v
CVSROOT: /home/oc/cvs
Module name: ethernet
Changes by: simons 03/07/09 13:53:43
Added files:
rtl/verilog : xilinx_dist_ram_16x32.v
Log message:
This file was not part of the RTL before, but it should be here.
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