LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Advertise
  • Mirrors
  • Logos
  • Contact us
  • Job Opportunity
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: OpenCores CVS Agent <cvs@w...>
    Date: Fri, 20 Jun 2003 13:51:32 -0100
    Subject: [cvs-checkins] can/rtl/verilog can_btl.v
    Top

    CVSROOT:	/home/oc/cvs
    Module name:	can
    Changes by:	mohor	03/06/20 13:51:32
    
    Modified files:
    	rtl/verilog    : can_btl.v 
    
    Log message:
    	Previous change removed. When resynchronization occurs we go to seg1
    	stage. sync stage does not cause another start of seg1 stage.
    
    
    
    
     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.