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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 28 May 2003 10:24:10 -0100
Subject: [cvs-checkins] mem_if/ ench/verilog/mem_if_bench.v ench/veril ...
CVSROOT: /home/oc/cvs
Module name: mem_if
Changes by: simons 03/05/28 10:24:09
Modified files:
bench/verilog : mem_if_bench.v mem_if_sdram_flash_sim_top.v
rtl/verilog : mem_if_registered_feedback.v mem_if_ro_top.v
mem_if_top.v
Log message:
Two separete wb interfaceces for register and memory access. The signal names changed to meet oc guidlines.
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