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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Wed, 7 May 2003 08:49:08 -0100
Subject: [cvs-checkins] vga_lcd/rtl/verilog vga_colproc.v vga_csm_pb.v ...
CVSROOT: /home/oc/cvs
Module name: vga_lcd
Changes by: rherveille 03/05/07 08:49:08
Modified files:
rtl/verilog : vga_colproc.v vga_csm_pb.v vga_cur_cregs.v
vga_curproc.v vga_defines.v vga_enh_top.v
vga_fifo_dc.v vga_fifo.v vga_pgen.v vga_tgen.v
vga_vtim.v vga_wb_master.v vga_wb_slave.v
Log message:
Fixed some Wishbone RevB.3 related bugs.
Changed layout of the core. Blocks are located more logically now.
Started work on a dual clocked/double edge 12bit output. Commonly used by external devices like DVI transmitters.
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