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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Thu, 14 Nov 2002 17:37:21 -0100
Subject: [cvs-checkins] ethernet/rtl/verilog eth_registers.v eth_top.v
CVSROOT: /home/oc/cvs
Module name: ethernet
Changes by: mohor 02/11/14 17:37:21
Modified files:
rtl/verilog : eth_registers.v eth_top.v
Log message:
r_Rst signal does not reset any module any more and is removed from the design.
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