Message

Reply | Reply all

Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

From: OpenCores CVS Agent <cvs@w...>
Date: Mon, 30 Sep 2002 16:34:03 -0100
Subject: [cvs-checkins] oc8051/ ench/verilog/oc8051_fpga_tb.v ench/ver ...

CVSROOT:	/home/oc/cvs
Module name:	oc8051
Changes by:	simont	02/09/30 16:34:03

Modified files:
	bench/verilog  : oc8051_fpga_tb.v oc8051_tb.v 
	rtl/verilog    : oc8051_acc.v oc8051_alu.v oc8051_alu_src1_sel.v 
	                 oc8051_alu_src3_sel.v oc8051_b_register.v 
	                 oc8051_comp.v oc8051_cy_select.v 
	                 oc8051_decoder.v oc8051_dptr.v 
	                 oc8051_ext_addr_sel.v oc8051_immediate_sel.v 
	                 oc8051_indi_addr.v oc8051_int.v 
	                 oc8051_multiply.v oc8051_op_select.v 
	                 oc8051_ports.v oc8051_psw.v oc8051_ram_rd_sel.v 
	                 oc8051_ram_sel.v oc8051_ram_top.v 
	                 oc8051_ram_wr_sel.v oc8051_reg1.v oc8051_reg2.v 
	                 oc8051_reg3.v oc8051_reg4.v oc8051_reg8.v 
	                 oc8051_rom_addr_sel.v oc8051_sp.v oc8051_tc.v 
	                 oc8051_top.v oc8051_uart.v 
	sim/rtl_sim/src/verilog: oc8051_ram.v oc8051_rom.v 
	                         oc8051_rom_fpga.v oc8051_uart_test.v 
	                         oc8051_xram.v 
	syn/src/verilog: oc8051_fpga_top.v oc8051_ram.v 

Log message:
	prepared header