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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Sat, 28 Sep 2002 07:18:55 -0100
Subject: [cvs-checkins] generic_memories/rtl/verilog generic_dpram.v
CVSROOT: /home/oc/cvs
Module name: generic_memories
Changes by: rherveille 02/09/28 07:18:55
Modified files:
rtl/verilog : generic_dpram.v
Log message:
Changed synthesizeable FPGA memory implementation.
Fixed some issues with Xilinx BlockRAM
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