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Message
From: OpenCores CVS Agent <cvs@w...>
Date: Thu, 19 Sep 2002 05:30:58 -0100
Subject: [cvs-checkins] ac97_ctrl/rtl/verilog ac97_cra.v ac97_defines. ...
CVSROOT: /home/oc/cvs
Module name: ac97_ctrl
Changes by: rudi 02/09/19 05:30:58
Modified files:
rtl/verilog : ac97_cra.v ac97_defines.v ac97_dma_if.v
ac97_dma_req.v ac97_fifo_ctrl.v ac97_in_fifo.v
ac97_int.v ac97_out_fifo.v ac97_prc.v ac97_rf.v
ac97_sin.v ac97_soc.v ac97_sout.v ac97_top.v
ac97_wb_if.v
Log message:
Fixed a bug reported by Igor. Apparently this bug only shows up when
the WB clock is very low (2x bit_clk). Updated Copyright header.
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