LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: OpenCores CVS Agent <cvs-checkins-agent@o...>
    Date: Wed, 28 Aug 2002 00:45:18 -0100
    Subject: [cvs-checkins] or1k/orp/orp_soc/rtl/verilog/or1200 or1200_cpu ...
    Top

    CVSROOT:	/home/oc/cvs
    Module name:	or1k
    Changes by:	lampret	02/08/28 00:45:18
    
    Modified files:
    	orp/orp_soc/rtl/verilog/or1200: or1200_cpu.v or1200_except.v 
    	                                or1200_sprs.v 
    
    Log message:
    	Removed some commented RTL. Fixed SR/ESR flag bug.
    
    
    
     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.