|
Message
From: OpenCores CVS Agent <cvs-checkins-agent@o...>
Date: Wed, 17 Apr 2002 13:16:45 +0200
Subject: [cvs-checkins] dbg_interface/rtl/verilog dbg_top.v
CVSROOT: /home/oc/cvs
Module name: dbg_interface
Changes by: mohor 02/04/17 13:16:45
Modified files:
rtl/verilog : dbg_top.v
Log message:
A block for checking possible simulation/synthesis missmatch added.
|
Browse
