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Message
From: OpenCores CVS Agent <cvs-checkins-agent@o...>
Date: Tue, 19 Feb 2002 17:56:14 +0100
Subject: [cvs-checkins] uart16550/rtl/verilog uart_defines.v uart_wb.v
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: mohor 02/02/19 17:56:14
Modified files:
rtl/verilog : uart_defines.v uart_wb.v
Log message:
Endian define added. Big Byte Endian is selected by default.
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