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From: OpenCores CVS Agent <cvs-checkins-agent@o...>
Date: Tue, 19 Feb 2002 17:32:39 +0100
Subject: [cvs-checkins] pci/ ench/verilog/pci_behaviorial_target.v enc ...

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/02/19 17:32:39

Modified files:
	bench/verilog  : pci_behaviorial_target.v 
	                 pci_regression_constants.v 
	                 pci_testbench_defines.v system.v 
	rtl/verilog    : pci_target32_interface.v pci_target32_sm.v 
	                 pci_target_unit.v wb_master.v 
	sim/rtl_sim/bin: artisan_file_list.lst ncsim.rc 
	                 xilinx_file_list.lst 
	sim/rtl_sim/run: clean ncsim.args ncsim.key ncvlog.args 
	                 run_pci_sim_regr.scr 

Log message:
	Modified testbench and fixed some bugs