LOGIN   :::   RECOVER PASS   :::   GET ACCOUNT    
Browse
  • Projects
  • Code (CVS)
  • Forums
  • News
  • Articles
  • Polls
  •  
    OpenCores
  • FAQ
  • CVS HowTo
  • Mission
  • Media
  • Tools
  • Sponsors
  • Mirrors
  • Logos
  • Contact us
  •  
    Tools
  • Search
      
  • Download Cores (CVSGet)
  •  
    More
  • Wishbone
  • Perlilog
  • EDA tools
  • OpenTech CD
  •  
    Navigation: All forums > Cvs-checkins > Message List > Message Post

    Message

    Reply | Reply all
    Date Prev | Date Next | Thread Prev | Thread Next Date Index | Thread Index

    From: OpenCores CVS Agent <cvs-checkins-agent@o...>
    Date: Mon, 28 Jan 2002 04:47:24 +0100
    Subject: [cvs-checkins] vga_lcd/rtl/verilog vga_wb_slave.v vga_wb_mast ...
    Top

    CVSROOT:	/home/oc/cvs
    Module name:	vga_lcd
    Changes by:	rherveille	02/01/28 04:47:23
    
    Modified files:
    	rtl/verilog    : vga_wb_slave.v vga_wb_master.v vga_vtim.v 
    	                 vga_top.v vga_tgen.v vga_pgen.v vga_fifo_dc.v 
    	                 vga_fifo.v vga_defines.v vga_csm_pb.v 
    	                 vga_colproc.v ud_cnt.v ro_cnt.v 
    
    Log message:
    	Changed counter-library.
    	Changed vga-core.
    	Added 32bpp mode.
    
    
    
    
     
    Copyright (c) 1999 OPENCORES.ORG. All rights reserved.