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Message
From: OpenCores CVS Agent <cvs-checkins-agent@o...>
Date: Thu, 17 May 2001 20:34:20 +0200
Subject: [cvs-checkins] uart16550/verilog UART_wb.v UART_TX_FIFO.v UAR ...
CVSROOT: /home/oc/cvs
Module name: uart16550
Changes by: gorban 01/05/17 20:34:19
Modified files:
verilog : UART_wb.v UART_TX_FIFO.v UART_top.v UART_test.v
UART_RX_FIFO.v UART_regs.v UART_defines.v
FIFO_inc.v
Added files:
verilog : UART_transmitter.v UART_receiver.v
Removed files:
verilog : UART_FIFO_t.v UART_FIFO.v ToDo.txt
Log message:
First 'stable' release. Should be sythesizable now. Also added new header.
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