|
Message
From: Martin Bosma<martinbosma@g...>
Date: Mon May 15 11:06:38 CEST 2006
Subject: [usb] USB 2.0 function core experience
Hello All!We're currently busy implementing the USB 2.0 function core into an Altera
Cyclone.
First we translated the verilog code into VHDL. The next step was to verify
the VHDL with the verilog.
That is almost done right now.
We are using 2 external PHY's: the USB3300 (SMSC) and the ISP1504 (Philips).
Both PHY's have an ULPI interface, and the OC IP core has an UTMI interface,
so we're busy making a wrapper.
The core has to communicate with an Altera NIOS II Softcore processor.
Now I was wondering if anyone has experience with this core and NIOS.
I have to write a driver but I don't really know how to do that.
At the PC side I also have to write a driver, perhaps I could use Jungo
WinDriver?
We are also trying to build a host controller, but this is too complex.
So, if there is anyone who has experience with this core and NIOS, please
share it with us.
Perhaps we can help you also...
Kind regards,
Martin Bosma
-------------- next part --------------
An HTML attachment was scrubbed...
URL: attachment.html
|
 |
Browse
