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Message
From: bknpk at hotmail.com<bknpk@h...>
Date: Fri Feb 3 23:30:23 CET 2006
Subject: [usb] usb2 function wishbone may trigger a false write
A false write may triggered with current implementation.
This is because wb_req_s1 may be re-asserted at an end of transaction.
I suggest the following:
// Sync WISHBONE Request
always @(posedge phy_clk)
//Pini
//wb_req_s1 <= wb_stb_i & wb_cyc_i;
wb_req_s1 <= wb_stb_i & wb_cyc_i & ~wb_ack_o;
at file
rtl/verilog/usbf_wb.v
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