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Message
From: Rudolf Usselmann<rudi@a...>
Date: Wed Dec 28 06:59:16 CET 2005
Subject: [usb] USB 2.0 core K chirp generation issue?
On Tue, 2005-12-27 at 21:50 +0100, johnp@p... wrote:
> According to the UTMI spec (page 31), the state of the TxReady pin
> is undefined in the TxWait state (see figure 12). Given that, I
> believe the following code will block the K Chirp generation if the
> UTMI interface has the TxReady signal asserted to a 1 by default.
>
> always @(posedge phy_clk)
> if(TxReady || tx_first) DataOut <= tx_data;
> else
> if(drive_k) DataOut <= 8'h00;
>
> I suspect it should actually be
> always @(posedge phy_clk)
> if(drive_k) DataOut <= 8'h00;
> else
> if(TxReady || tx_first) DataOut <= tx_data;
>
> Any thoughts on this?
>
> John Providenza
I think the change should be ok.
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis
****** Certified USB 2.0 HS OTG and HS Device IP Cores ******
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