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Message
From: pertierr@p...<pertierr@p...>
Date: Sat Jan 29 01:53:07 CET 2005
Subject: [usb] About USB 2.0 Verilog Core
I've been trying to get this core to work for a while now in a very simple
application. I have a couple of simple questions:
What exactly are the known problems with the core? I am experiencing
time-out problems when waiting for the DATA0 after a SETUP, and in
waiting for the ACK after sending DATA1 response to IN. For example, i
had to increase USBF_TX_DATA_TO_VAL_FS to 8'd75(from 8'd36)
otherwise it would time out when waiting for DATA0 following a SETUP
token!
Has anyone here had success in getting it to work? My goal is to
implement a 1-IN endpoint system, so far i am synthesizing it with only
the control endpoint. My function controller is just another block inside
the FPGA.
If anyone has had success with it, i'd sure like to hear it.
Thanks!
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