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Message
From: Rudolf Usselmann<rudi@a...>
Date: Mon Jan 17 19:41:21 CET 2005
Subject: [usb] USB 1.1 Device Core Endpoint Clarification
On Sat, 2005-01-15 at 11:45 +0100, ramachandiran.v@s... wrote:
> Dear USB People,
>
> I have a Question regarding USB 1.1 Endpoint .
>
> First Let me describe what I'm doing using USB Core.
>
> I developed PS2 Keyboard to USB application using USB 1.1 core. I wrote PS2
> Interface logic and gluelogic to store ASCII value of the Pressed Key in Endpoint 5.
> [ Endpoint 5 is configured as IN , INTERRUPT with max of 64 Byte transfer. I use
> Windriver USB software to read USB Port.
>
> ep5_cfg = `INT | `IN | 14'd0001
>
> Device Enumeration is taking place properly and i could see all the endpoints with the
> same setup mentioned in usb1_rom.v file.
>
> The Problem i'm facing is like , what ever the data i type in Keyboard , It is read and
> displayed TWICE. I checked the behavioral simulation and saw that the data is stored
> in Endpoint FIFO only once with WE for FIFO is kept asserted for 1 Clock Pulse.
>
> I even tried to store the data into Endpoint FIFO continuously and then Invoked
> Windriver software. Then also each character is displayed TWICE [ i.e., . i Typed
> rama ..But i received as ..rraammaa ].
>
> Is this the Problem with INTERRUPT Transfer Mechanism the way i configred.
> or
> Could it be the Problem of Windriver Software ?..
>
> Can anyone clarify me where exactly the Problem and how can i overcome this ?
>
> It would be grate Helpful for me.
>
> Thanks in Advance ,
> Ramachandiran.V
Replace your keyboard with a 3 bit counter. Add 0x30 to the
counter output and write that to the FIFO. If you see a
continues 0...7 with out any repeats, the problem is in your
keyboard interface/interpretation logic. If you see something
like 001122..77 than there is a problem with the USB IP Core/FIFO ...
Regards,
rudi
=============================================================
Rudolf Usselmann, ASICS World Services, http://www.asics.ws
Your Partner for IP Cores, Design, Verification and Synthesis
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