OPENCORES.ORG

Hi,

hi michal,
I think this might help you.
For full-/low-speed transactions, the timer starts
counting on the SE0-to-‘J’ transition of the EOP
strobe and
stops counting when the Idle-to-‘K’ SOP transition is
detected. For high-speed transactions, the timer
starts
counting when the data lines return to the squelch
level and stops counting when the data lines leave the
squelch level.
If a response is not received within this worst case
timeout(18 bit timres for FS), then the transmitter
considers that the packet transmission has failed.

Then the concerned register bit is changed and the
next  Token packet is sent.

pranav

> Hi,
> I mean resetting/starting timeout timer not USB
> reset. 
> I understand spec like that:
> For eg. when device receives setup token in control
> transfer it expects 
> data0 packet to arrive before timeout after setup
> token(18 bit times for 
> Full Speed). So, it starts timeout timer after
> succesfull reception of 
> SETUP (ie after EOP = SE0 to J transition) and check
> if timout occurs.
> 
> I am not sure, but timeout timer maybe should be set
> to value 18 bit 
> times minus SETUP packet length duration time in
> this example, because 
> timer starts after SETUP packet is received.
> Am i right?
> 
> Michal
> 
> 
> 
> > > I would like to ask about timeout values in usb
> 2.0 core, why 
> > these 
> > > are 
> > > 622 ns FS(7.5b times) and 400 ns HS (192b
> times)? 
> > > Shouldn't these be 18 bit times in FS and 816
> bit times in HS 
> > as 
> > > stated 
> > > in 7.1.18 of usb spec (end to end delay)? 
> > > And how timeout is checked? Is timeout counter
> started when 
> > > linestate 
> > > enters squelch level (or SE0 to J transition for
> FS) and reset 
> > when 
> > > linestate leaves squelch (or J to K transition
> for FS), when 
> > device 
> > > waits 
> > > for data or response from usb host)? 
> > > 
> > > 
> > 
> > 
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/usb
> 

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