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Message
From: Rudolf Usselmann<rudi@a...>
Date: Fri May 28 06:18:55 CEST 2004
Subject: [usb] Ask a help on (USB2.0)
On Fri, 2004-05-28 at 01:12, Brian Adams wrote:
> I did a little testing of the USB 2.0 core a while ago, and also
> noticed the usb_vbus_pad_i problem. The Verilog code expects
> ubs_vbus_pad_i to be a negative true. (don't ask me why, seems incorrect
> to me) So, you can either tie it off low, or invert it once it comes
> into your chip. (I did the latter)
[SNIP]
> Unfortunately (just when it was getting interesting) I had to shift to
> something else and won't be able to go back for a while. I don't know
> if any of this is helpful to anyone, but here it is anyway.
>
> All of my testing was done in FS. For some reason my HS Speed
> Negotiation failed and reverted to Full Speed. (have to check that out
> too, some day)
>
> Brian
Hi Guys,
I am in the process of rewriting major portions of the
USB 2.0 Device IP.
This will take a while. The goal is to build a FPGA
prototype and take it through USB certification as well.
Brian form SMSC was kind enough to donate a very nice PHY
from SMSC, the GT3200. It is a fully UTMI complaint PHY.
Since I'm doing everything alone this will take time.
Perhaps somebody would like to help with a test-bench ?
You must be serious about it - it takes a lot of time
and work. I can provide a lot of guidance.
The New version of the core will be release under a NEW
LICENSE. It will now be free ONLY for Educational and
Personal uses. It still will be Open Source. Reason for
that is that I am not getting any help at all. From the
10(+/-) people who offered to write a test bench in the
last 3 years, NOBODY ever did.
I will not release my own test bench - don't even bother
asking. I can't handle the tech support for the core, I'm
not going to do the same with the test bench. All requests
for the test bench will be redirected to /dev/null. Sorry,
no other way here ...
If you guys find any bugs, please email (or cc) them to
me directly as well.
Regards,
rudi
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