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From: M. AbuKhater<perocletos@y...>
Date: Sun May 9 13:43:27 CEST 2004
Subject: [usb] usb1.1 Simulation
Hi all
I was trying to do some simulation on the USB1.1 core design, it has its own test bench verilogs. am using the Model sim, but it seems not working properly.
has any one tried to do simulation on this core, whats the right procedure for that ?

Abukhater


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