|
Message
From: Steve Vu<SVu@S...>
Date: Wed Mar 17 18:47:06 CET 2004
Subject: [usb] dribble bits before or after EOP?
7.1.9.1 Full-/low-speed
Full-/low-speed signaling uses bit stuffing throughout the packet
without exception. If the receiver sees seven
consecutive ones anywhere in the packet, then a bit stuffing error has
occurred and the packet should be ignored.
The time interval just before an EOP is a special case. The last data
bit before the EOP can become stretched by
hub switching skews. This is known as dribble and can lead to the case
illustrated in Figure 7-33, which shows
where dribble introduces a sixth bit that does not require a bit stuff.
Therefore, the receiver must accept a packet
for which there are up to six full bit times at the port with no
transitions prior to the EOP.
11.7.1.1 Squelch Circuit
Because of squelch detection, the initial bits of the SYNC field may not
be seen in the rest of the repeater.
At most, 4 bits of the SYNC field may be sacrificed in the entire
repeater path.
The squelch circuit may take at most 4 bit times to disable the repeater
after the bus returns to the Idle state.
This results in bits being added after the end of the packet. This is
also known as EOP dribble and up to
4 random bits may get added after the packet by the entire repeater
path.
All,
The first section mentions that dribble can happen before the FS/LS EOP
and the second section mentions that dribble can happen at the end of HS
EOP. I just want to confirm my suspicion here. Is because the EOP is not
data in FS/LS but is data in the HS and only data can have dribble
added?
Thanks in advance,
Steve
-------------- next part --------------
An HTML attachment was scrubbed...
URL: attachment.htm
|
 |
Browse
