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Hi,

Hi,
Yes, modding the current UMTI interface is also better from a logic
usage perspective point of view. I chose to write the small module
interface,
because the purpose of my testbench is to test the core as it was provided
by Rudi.

As soon as I have a working version of the phy module I will send it to you
... probably in a couple of days. By then, I also hope to have the small
module
interface ready as well ...

Regards,
Ovidiu Lupas.

----- Original Message ----- 
From: <wesselin@n...>
To: <usb@o...>
Sent: Wednesday, March 10, 2004 9:40 AM
Subject: Re: [usb] UTMI / PHY help please

> Hi,
>
> that's great news!
> i'm currently modding the umti interface so that it can interface with the
> 1501. learning basic verilog proved not to be too much of a hastle....
> i first thought of a module between the phy and core, but it seemed to
> me that modding the utmi if itself would be an easier task.
>
> maybe while you are coding the phy, i can provide the adapted utmi
> interface? (or have you allready begun coding the module inbetween as
> well?)
>
> maybe i can do some prerelease verification or beta testing or whatever
> you would like to call it for you.
>
> Regards,
>
> Egwin Wesselink
>
>
> ----- Original Message ----- 
> From: Ovi Lupas<olupas@o...>
> To:
> Date: Wed Mar 10 15:05:50 CET 2004
> Subject: [usb] UTMI / PHY help please
>
> > Hi,
> >
> > I am working right now on a USB 2.0 testbench. In my testbench,
> > I plan to interface the USB2.0 core with a ISP1501 behavioral model
> > that I am coding right now.
> > The interface between the two will be a small synthesizable module
> > written in Verilog that will be also published.
> > But I still have to code a while and to check it before releasing
> > it ...
> > Regards,
> > Ovidiu Lupas.
> >  ----- Original Message ----- 
> >  From: wesselin@n...
> >  To: usb@o...
> >  Sent: Thursday, March 04, 2004 8:22 AM
> >  Subject: *bump* [usb] usb2 core / PHY ISP1501
> >  ----- Original Message ----- 
> >  From:
> >  wesselin@n...<wesselin@n...>
> >  To:
> >  Date: Thu Feb 26 13:07:12 CET 2004
> >  Subject: [usb] usb2 core / PHY ISP1501
> >  > hello everybody,
> >  >
> >  > for our (my colleague and i) graduation project we need to
> >  > implement a usb 2 (device) link in a prototyping system. This
> > system consists
> >  > of a
> >  > philips ISP1501-01 IC and an FPGA. We intended to use the usb
> > 2
> >  > core
> >  > by rudi in the fpga, since the documentation stated it
> > supported
> >  > the
> >  > 1501.
> >  > However, the 1501 does not seem to comply with the core's
> > UMTI
> >  > interface type. The core uses a double (tx/rx) 8 bit wide
> > interface
> >  > @ 60
> >  > MHz, whereas the 1501 can only be used with the 16 bit wide
> >  > (bidirectional) interface @ 30 MHz. BTW i hope somebody can
> > prove
> >  > me
> >  > wrong here... :-)
> >  > Hence i would like to know if somebody has a workaround for
> > this
> >  > problem, or do we need to rewrite the entire core for a 16
> > bit wide
> >  > bus?
> >  > Has anybody actually used the 2.0 core succesfully for that
> > matter?
> >  > We are not native verilog developers ( we were tought VHDL)
> > though
> >  > it
> >  > should probably not be a problem to learn that language...
> >  > If nobody has used this core in conjunction with the 1501 we
> > would
> >  > maybe like to contribute by either writing a workaround or
> >  > modifying the
> >  > core so that it can work with both 8bit 60 MHz or 16 bit 60
> > MHz
> >  > (only if
> >  > that option proves to be not too much of a hastle).
> >  > Regards,
> >  > Egwin Wesselink
> >  >
> >  >
> >  _______________________________________________
> >  attachment.htm
> >
> >
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>