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Message
From: Rudolf Usselmann<rudi@a...>
Date: Fri Mar 5 18:31:41 CET 2004
Subject: [usb] Suspend mode and FPGA:s
On Fri, 2004-03-05 at 23:17, wesselin@n... wrote:
> first of all thanks for the quick reply
>
> The info you gave me is very usefull, i know now i wont be able to
> implement suspend/resume.
> i will have to be working on an xilinx virtex II 8000. Though that's not
> that big of a punishment :-), it draws too much power.
>
> i think i'm gonna NOT suspend my device at all (though not up to spec)
> since it isn't powered by the usb bus. (for a quick reference to my
> project (if you're interested) see the bumped post i did couple of days
> ago). If i wont suspend it, it'll respond to resume signaling nonetheless
> since my core's still up and running...right?
>
> i'll have to check whether it is at all possible to not suspend a device,
> though in my case i think there aren't too many other options.
All that suspend means is that you must not draw any power
from the USB bus. If you are self-powered, you can bake pizza
on the side and be compliant. And, yes, you should follow the
protocol, and perhaps signal to your local logic that you have
receives a suspend event. After all that means that you will
not be getting any traffic from the usb bus, so you might want
to 'notice' that event. Same for resume signaling, you should
'notice' the event, and get back in to the 'working' state, but
since you are self powered, you don't have to turn off power or
even place the PHY in to the suspend mode.
If you do suspend the PHY, you must have a combinatorial path to
wake it up, as the clock will be turned off. That is usually done
by wathing the LineStat signals (which become combinatorial path
inside the PHY when you suspend the PHY). If the state of LineState
changes, you automatically start wake up and resume ...
> quote
> > What exactly is the wake up criteria in the USB spec? It would be
> > an
> > unusual circuit that could do significant processing and still have
> > very
> > low power like this (500 uA). But then I guess it is not
> > impossible. Does
> > the circuit wake up on the first signal transition on the USB bus?
> unquote
>
> i think i wont be able to implement the suspend mode because of this
> too, since even when the phy wakes up on the first signal transition, my
> DCM in the FPGA will still need time to lock.
>
> i just found out my phy isn't bus powered too so not suspending the
> device wont be a problem i guess...
>
> Regards,
>
> Egwin Wesselink
Cheers,
rudi
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