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Message
From: wesselin@n...<wesselin@n...>
Date: Fri Mar 5 16:10:17 CET 2004
Subject: [usb] Suspend mode and FPGA:s
hello all,quote:
> I think the core has to be up and running if it should be able to detect
> resume signaling from the hub? This does not make it easier though!
unquote.
i kinda have the same problem:
since in my case the core will be running on a clock provided by the
phy, putting the device in suspend will disable the clock, and thus the
core wont be able to detect any resume signaling as well....right?
will it be sufficient to just reset the core and usb bus when the clock is
up & running after the bus (i will be using a clock manager in the fpga ->
no problem generating a reset)?
OR even better, will it be possible for me to tie suspend to the phy to 0
all the time? i want my device to work, it doesn't have to be up to the
usb20 spec.
if somebody can figure out what my options are, i would really
appreciate some help on this point.
thanks in advance,
regards,
Egwin Wesselink
----- Original Message -----
From: a_karlstrom@y...<a_karlstrom@y...>
To:
Date: Fri Mar 5 12:37:41 CET 2004
Subject: [usb] Suspend mode and FPGA:s
> Thanks Rick!
>
> I think the core has to be up and running if it should be able to
> detect
> resume signaling from the hub? This does not make it easier though!
> Maybe I have to choose an integrated usb device controller
> instead...
> Anders Karlstrom
> ----- Original Message -----
> From: Rick Collins<opencores.usb@a...>
> To:
> Date: Thu Mar 4 20:40:09 CET 2004
> Subject: [usb] Suspend mode and FPGA:s
> > At 11:24 AM 3/4/2004, you wrote:
> > >Hi!
> > >
> > >I would like to know how to implement an IP core in a FPGA
> or
> > CPLD and
> > >still meet the requirement of maximum 500uA current
> consumprion
> > in
> > >suspend mode. Is this really possible or are the cores not
> > intended for
> > >bus powered devices? As far as I know there are no
> FPGA/CPLD
> > that
> > >can run on 500uA.
> > >I'm thankful for any help!
> > I think you are right about the FPGAs, there are none with
> idle
> > currents
> > this low. But you can always shut off the power to the FPGA
> and
> > reload it
> > when you need to power it back up.
> > There are CPLDs with idle currents in the low uAs. I recall
> looking
> > at a
> > Coolrunner part, powered from 3.3 volts which had an idle
> current
> > low
> > enough that the quiescent current of the LDO was higher than
> the
> > CPLD! I
> > think the XCR3512 was around 10 to 20 uA or so. Can you fit
> your
> > design in
> > a CPLD though?
> > Rick Collins
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design URL http://www.arius.com
> > 4 King Ave 301-682-7772 Voice
> > Frederick, MD 21701-3110 301-682-7666 FAX
> >
> >
>
>
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