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Message
From: Rick Collins<opencores.usb@a...>
Date: Thu Mar 4 20:40:09 CET 2004
Subject: [usb] Suspend mode and FPGA:s
At 11:24 AM 3/4/2004, you wrote:
>Hi!
>
>I would like to know how to implement an IP core in a FPGA or CPLD and
>still meet the requirement of maximum 500uA current consumprion in
>suspend mode. Is this really possible or are the cores not intended for
>bus powered devices? As far as I know there are no FPGA/CPLD that
>can run on 500uA.
>I'm thankful for any help!
I think you are right about the FPGAs, there are none with idle currents
this low. But you can always shut off the power to the FPGA and reload it
when you need to power it back up.
There are CPLDs with idle currents in the low uAs. I recall looking at a
Coolrunner part, powered from 3.3 volts which had an idle current low
enough that the quiescent current of the LDO was higher than the CPLD! I
think the XCR3512 was around 10 to 20 uA or so. Can you fit your design in
a CPLD though?
Rick Collins
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
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