|
Message
From: antti@c...
Date: Mon, 17 Nov 2003 08:52:24 +0100
Subject: Re: [usb] USB Test Bench getting hung...
the USB 1.1 Func testbench
1 works out of box (no changes) with free iverilog simulator, try this
2 it should also work with modelsim (not sure if I have tested it), at any
case no modifications should be made to the testbench. sure modelsim
and iverilog do have sometimes different problems with same rtl code.
3 it works out of box in FPGA with xilinx XST synthesis
4 it does not support LS (low speed) USB at all
antti
----- Original Message -----
From: horizon_temp@y...
To: usb@o...
Date: Mon, 17 Nov 2003 08:17:49 +0100
Subject: [usb] USB Test Bench getting hung...
>
>
> I am trying to integrate the following USB files as part of my SoC.
> I need to make use of a Low-Speed USB 1.1 device that is just used
> for
> the purpose of downloading some software from the Host Computer
> onto
> a device.
>
> I was trying to use the test bench that was included with the IP
> Package developed by Mr Rudolf. I was able to compile the project
> in
> ModelSim.
>
> But on simulating the test bench, it gave some $DISPLAY errors. So
> changes were made to the orignal test bench to overcome errors like
> Length Mismatch and ACK . Finally the testbench was getting hung in
> UTMI_recv_pack task waiting for a ACK from the device. The
> message "Getting Descriptor...." is displayed.
>
> After hours and hours of tracing throught the "entire code" and
> figuring
> out how the data was being passed from the testbench onto the core
> and the endpoints, - it appeared that there was some error in the
> Function Address field. Several permuations and combinations were
> tried! Finally the Address was changed to point at "0". But it
> does not
> seem right!
>
> The files have been posted at - www.pitt.edu/~ksg3/usb.tar.gz
>
|
 |
Browse
