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Message
From: "Marc Reinig" <mreinig@p...>
Date: Fri, 24 Oct 2003 13:06:09 -0700
Subject: RE: [usb] USB 1.1 PHY, DPLL question
I don't know why you think that +/- 20% are possible.
In an IC design, part of the designers job is to match performance of
circuits that need to be held to certain tolerances. On a give die, the
performance characteristics of the transistors are going to match very
closely. The total capacitive load is harder to balance, but, after all,
that's what they get paid for.
Marc Reinig
System Solutions
> > If I remember correctly, USB specifies 0.5% error for the
> > clock, so how can the edges of DP and DM be off by 40% ?
>
> see above, I would estimate that edge jitter +/-20% are possible.
>
> and yes it can be - USB spec says clock error, but nothing about
> the jitter after single ended receivers. If you look at the internals
> of USB11T1A or compatible USB tranceiver then you see 3 different
> receivers one each for DP/DM and one for both (The differential one).
>
> the single ended receivers are sometimes also drawn as having
> smith trigger funtionality ie built in glitch cancellation, I can easily
> believe that the single ended signal and differential receiver signals
> differ a lot, what they also do.
>
> this may vary a little depending on the tranceiver chip in use
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