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Message
From: Arius - Rick Collins <opencores.org@a...>
Date: Mon, 13 Oct 2003 16:07:21 +0200
Subject: Re: [usb] Size of USB2.0 implementation
Thanks for the info. That is a large design. It is over half the
chip I was looking at using, the XC3S400. Do you think there are any
features that can be reduced significantly if I work on them? I would
like to get this down to roughly half the size minus the bus
interface, about 2000 FF/ 1000 slices. Do you expect this is at all
feasible?
BTW, I didn't make the second post because I was getting impatient for
an answer. I sent the first by email and did not see it in the list.
I thought that the email did not make it. The second message was
done directly at the web site.
----- Original Message -----
From: Rudolf Usselmann <rudi@a... >
To: usb@o...
Date: Mon, 13 Oct 2003 20:16:25 +0700
Subject: Re: [usb] Size of USB2.0 implementation
>
>
> On Sat, 2003-10-11 at 23:13, Arius - Rick Collins wrote:
> > I am looking at the size required for an FPGA I am using in a
> new
> > design. It will have several interchangeable interfaces which
> will include
> > a USB2.0 module. I can't seem to find any info on the
> implemented size for
> > the opencores USB2.0 design. Does anyone have a ball park
> number I can
> > work with? How many FF/LUTs can I expect the USB2.0 design to
> use?
>
> Sorry, I meant to reply to this earlier, but it slipped my
> mind.
>
> For a "xcv400e, package fg676, speed -7":
>
> Number of External GCLKIOBs 2 out of 4 50%
> Number of External IOBs 233 out of 404 57%
> Number of LOCed External IOBs 0 out of 233 0%
> Number of SLICEs 1880 out of 4800 39%
> Number of GCLKs 2 out of 4 50%
>
> I believe this was with 4 endpoints.
>
> > How about the UART 16550 core? Anyone have any data on the
> implemented
> > size of that?
> >
> > I know that the numbers will vary depending on the chip and
> tools
> > used. But I am just looking for a ball park number.
> >
> > Thanks,
> >
> >
> > Rick Collins
>
> Regards,
> rudi
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