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Message
From: Jiang daosan <jiangdaosan@2...>
Date: Sun, 31 Mar 2002 20:14:19 +0800
Subject: Re: [usb] some question about the code of the USB function core
Hi, rudi:
On 2002-03-31 13:22:00 You wrote:
>On Saturday 30 March 2002 02:40 pm, you wrote:
>> Hi,Rudi and all:
>>
>> I have some questions about the USB function core.
>> The first is that how can I re-simulate the core as I cannot
>> find anything in the dictory of bench. I want to learn how
>> to get a full simulation about the core.
>
>How about writing a test bench ???
Exactly I don't know how to write a good and full coverage testbench
now. That skill is what I want to learn. Can someone help me about that?
Any advice and papers are welcomed. Maybe I can have a try. :)
>
>I've been asking for someone to help to write a test bench, but
>nobody wants to do it ...
>
>> The second is that I have seen some code in the module of the core
>> like that following :
>>
>> always @(posedge clk)
>> clr_sof_time <= #1 frame_no_we;
>> ~~~~~ that means to assign the value after one unit
>> time
>>
>> In my opinion, to add one unit time delay in the code is to minimize
>> the difference between the RTL simulation and the synthesized gate-level
>> simulation. But that code may not be supported by the synthesis tools.
>> Is that true ? How can I change the core into synthesisable ?
>
>No this does not bring rtl closer to gate level simulations. Timing
>will always differ depending on your technology. The "#1" is really
>absolutely meaningless. The only reason I like to add them is
>because it makes debugging of rtl so much easier.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Why did the delay in the code make debugging much easier ?
I don't understand what do you mean exactly. Could you explain that more ?
Thanks.
>
>This core is absolutely 100% synthesizable. Every synthesis tool
>will ignore the "#1".
>
>rudi
>
>> Thanks for your answer.
>>
>> Best regards.
>>
>>
>> Jiang daosan
>> jiangdaosan@2...
>
>
>
Jiang daosan
jiangdaosan@2...
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