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Message
From: "Benoit Côté" <benoit.cote@p...>
Date: Wed, 27 Mar 2002 07:28:21 -0500
Subject: Re: [usb] clk of the SIE
hi,
LS only and FS only implementation drives a 4X CLK to the SIE (6 MHz ; 48
MHz respectively).
8-bits implementatin speaking, FS/HS gives a constant CLK of 60 MHz (30MHz
for 16-bit imp) in both FS and HS modes (60M x 8bit = 480Mps).
Switching mode doesn't affect the CLK output by the PHY. The SIE handles the
Rx-Tx data lines accordingly.
----- Original Message -----
From: "ZhiPLiu" <zpingl@2...>
To: <usb@o...>
Sent: Tuesday, March 26, 2002 11:15 PM
Subject: [usb] clk of the SIE
> Hi all,
>
> Is the clk of SIE the output clk of PHY chip? and but on the
> UTMI specification(version 1.05) the output clk is 48Mhz in fs only
> operation,the data rates is 12M.why the output clk is 48Mhz. "A 'fs ony'
> implementation of the utm would provide 32 clk cycles per byte time" is
> in the page 22 of the utmi specification,but "the clocking of a hs/fs utm
> in fs only and ls only implementations,except that for fs only and ls only
> implementations there are only 8 clk cycles per byte time" is on the
> page 25. do they conflict.
>
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