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Message
From: ZhiPLiu <zpingl@2...>
Date: Wed, 27 Mar 2002 05:17:49 +0100
Subject: Re: [usb] frequency of operation
----- Original Message -----
From: Rudolf Usselmann <rudi@a... >
To: usb@o...
Date: Wed, 13 Mar 2002 18:57:08 +0700
Subject: Re: [usb] frequency of operation
>
>
> On Wednesday 13 March 2002 01:59 pm, you wrote:
> > Hi All,
> >
> > In a usb2.0 according to standards, the max data rate can be
> > 480Mbps, That means for a serial bus the frequency at which
> the
> > circuit should work is 480MHz. This is not physible.....
>
> Why not ? It's not possible to implement the physical interface
> section in todays FPGAs but an easy task for an ASIC. An
Hi all,
Is the clk of SIE the output clk of PHY chip? and but on the
UTMI specification(version 1.05) the output clk is 48Mhz in fs only
operation,the data rates is 12M.why the output clk is 48Mhz. "A 'fs ony'
implementation of the utm would provide 32 clk cycles per byte time" is
in the page 22 of the utmi specification,but "the clocking of a hs/fs utm
in fs only and ls only implementations,except that for fs only and ls only
implementations there are only 8 clk cycles per byte time" is on the
page 25. do they conflict.
> alternative is to use an external PHY chip. This is what my
> USB 2.0 Function core does. I hope I can add a USB 1.1
> compliant PHY soft core in the future.
>
> By the way that is "feasible" ...
>
> > How can I design the circuit for lesser frequency.
>
> What you probably want is USB 1.1, which defines data rates
> at 1.5 and 12 Mbits per second.
>
> > Thanx in advance.
> >
> > Prashant.
>
>
> rudi
>
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