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Message
From: utada23@h...
Date: Mon, 18 Feb 2002 13:05:32 +0100
Subject: Re: [usb] timing diagram request...
hi!...Its me again...to anybody who has seen the usb core...I have
questions regarding the endpoints and how the SSRAM is divided among
them...does memory mapping applies to this?... or the whole SSRAM is
accessible to all endpoints?...or each endpoints has its own SSRAM?...I'll
be waiting for your responds...thanks!
----- Original Message -----
From: utada23@h...
To: usb@o...
Date: Sun, 17 Feb 2002 04:10:30 +0100
Subject: [usb] timing diagram request...
>
>
> Mr Rudolf Usselmann,
>
> Hello!...I'm new here...and I'm currently studying your usb
> core...good
> job!...I hope you don't mind if I request a timing diagram of the
> wishbone IF...particularly the DMA transfer...this will be greatly
> appreciated!
>
>
> regards,
> utada
>
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