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Message
From: make_u_play at yahoo.com<make_u_play@y...>
Date: Fri Oct 26 14:26:13 CEST 2007
Subject: [pci] Rookie questions about PCI
Thanks heeps all this info is really helpful!> BTW are you producing your own board? Or are you going to use a
> PCI/PCIe FPGA evaluation board for this?
Initially I am planning on getting a generic board with a PCI connector
and using it but I plan on designing my own board using Altium designer
once I have a working prototype. I know a few people that will probably
chip in so I can spread the cost of having a board made + I know a
place in china that will make a board with the following spec for about
$700 setup + $120 a board (1 - 10 boards) and I was planning on
getting Dayang to mount all the BGA and QFN packages for me.
Layers 10
Board Size (width) 200 mm
Board Size (height) 120 mm
Min. Tracing/Spacing 0.07 mm
Min. Annular Ring 0.10 mm
Smallest Holes 0.10 mm
> An image is a contiguous block or window of memory or I/O space -
> see BAR in PCI documentation.
Ok I was having a look at http://www.fpga4fun.com/PCI2.html. It says
"The disadvantage of the IO space is that it's small (limited to 64KBs on
PCs, even if PCI supports 4GBs) and pretty crowded. " I also had a look
at the I/O space addresses on my PC and it is crowded and limited to a
max address of xxxxx....FFFF. Can you explain the difference between
I/O space and memory space from a hardware and software point of
view. Basically what I want to know is from the computers perspective
what is so different between I/O space and memory space? From what I
can see they are pretty much the same sort of thing i.e. I access both
by an address and read or write data to both. What are the unique
aspects of each that make them special and different?
With regard to the BAR I do recall having read about it a few years ago.
I will search through the documentation with that in mind as soon as I
get a copy. But to clarify the base address register is the register(s) in
the config space that is updated by the host pc telling the card where
the assigned memory space has been mapped to correct? Also how
does the card know how much memory space has been assigned to it?
Now say infact that I wanted to have 4GB of RAM on my PCI card. I
choose 4GB since its well over the direct addressing limit for a 32 bit
system. So if I want to access all of the 4GB in which there is data how
will I go about this? There is a limit to how much memory space I can be
assigned am I correct? and beyond this I will have to impliment some
type of indirect addressing or paging scheme where I tell my PCI card to
switch between two 2GB ram sections?
>Typically your application would have a user-mode buffer into which
> data is read from your card by the application. Without DMA, you'd
> simply be reading from memory or I/O space mapped by your card and
> writing to your application buffer. With DMA, you'd supply the physical
> address of the application buffer to the DMA engine - whose registers
> are also mapped into memory or I/O space on your card - and then
> tell it to start transferring. Once the DMA is finished, you could get a
> PCI interrupt, or you could poll a status register in the DMA engine.
What exactly is a user-mode buffer?
Also by application buffer do you just mean an array in my program and
nothing special right?
When you say the DMA's registers are mapped to memory or I/O space
that is simply so I can update the destination address for the transfer
right? (The only DMA I have delt with is on an MSP430 microcontroller
where you supply a source address, dest address and #bytes or words
+ trigger source etc... and it finishes the transaction and calls an
interrupt is it exactly the same thing with a PC?)
Many thanks,
Greg
----- Original Message -----
From: Mark McDougall<markm@v...>
To:
Date: Fri Oct 26 05:41:23 CEST 2007
Subject: [pci] Rookie questions about PCI
> make_u_play at yahoo.com wrote:
>
> > I read some of the datasheets for the bridge and was unclear
> about what
> > is ment by Image. There are references to you can have several
> images.
> An image is a contiguous block or window of memory or I/O space -
> see BAR
> in PCI documentation.
> > Also at this point would you suggest I continue research into
> PCI or
> > would looking at PCI express be a better option? In some of
> the
> > previous posts this months there has been discussion about
> xilinx
> > having devices with hardcores for pci express, is this
> something like a
> > peripheral unit eg. adc on a microcontroller if I can use that
> > analogy, which I simply read and write to or is it just a
> permanently
> > wired up IP core to which connections are made ie It has some
> preset
> > parameters and is not as configurable.
> I'm not overly familiar with Xilinx PCIe offerings, or indeed PCIe
> itself,
> though I have done some research into it for a customer. A
> hard-core is a
> fixed functional block, but it should still be quite configurable.
> I
> suspect for your purposes, functionally a hardcore would be
> perfectly
> adequate.
> Whether PCI or PCIe is the way to go would depend on what your
> requirements are. If your card won't be produced commercially, and
> you
> have lower bandwidth requirements, personally I'd stick with PCI.
> Why? You
> don't have to worry about gigabit transmission on your PCB, and I
> suspect
> that PCI is easier to debug on both a hardware and software level.
> BTW are you producing your own board? Or are you going to use a
> PCI/PCIe
> FPGA evaluation board for this?
> > I have my own PCI card that I put into a PC. On the PC side I
> have an
> > application written in C# for example the role of which is to
> process
> > the sampled data and graphically display it for the user. Once
> the
> > application is started up it sends commands to the PCI card
> (card is
> > now a target) the card inteprets the information and begins
> its data
> > acquision. The acquired data is written to onboard DDR(2)
> SDRAM.
> That's certainly feasible, yes! I know nothing about C# but I
> assume you'd
> need some sort of driver - even if generic - to talk to your card.
> You'd
> do so by reading/writing registers mapped by your card into memory
> or I/O
> space.
> > Do I need to make an interrupt request to the host PC to get
> access to
> > the bus or do I wait for there to be no traffic? (or is this
> handled
> > by the bridge?)
> Bus arbitration is handled transparently by the arbiter on the PC
> host and
> the PCI core in your card - you simply need to request a transfer
> (eg.
> memory read/write request to PCI space mapped by your card) and
> it'll
> happen once the bus is available.
> > Once able to transmitt data I setup a DMA engine to shift the
> massive
> > amount of sampled data to the host.
> Yes, but now you're mastering so your core would have to have that
> capability (which opencores PCI does).
> > Can you explain how the data is handled when it reaches the
> host? I'm
> > completely new to the PCI interaction with the software side
> so this is
> > a grey area at the moment.
> Typically your application would have a user-mode buffer into which
> data
> is read from your card by the application. Without DMA, you'd
> simply be
> reading from memory or I/O space mapped by your card and writing to
> your
> application buffer. With DMA, you'd supply the physical address of
> the
> application buffer to the DMA engine - whose registers are also
> mapped
> into memory or I/O space on your card - and then tell it to start
> transferring. Once the DMA is finished, you could get a PCI
> interrupt, or
> you could poll a status register in the DMA engine.
> BTW there is also an opencores DMA engine.
> > Also the 100MB/s is not a major hassel since I will only be
> sampling
> > for short periods and storing to ram I intend to have on the
> board,
> > before sending it across to the PC.
> So PCI should suffice then.
> Regards,
> --
> Mark McDougall, Engineer
> Virtual Logic Pty Ltd, <http://www.vl.com.au>
> 21-25 King St, Rockdale, 2216
> Ph: +612-9599-3255 Fax: +612-9599-3266
>
>
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