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Hi,

Hi Jeremy!
Infos look OK to me, as you have
WISHBONE Slave interface's control signals
tied off to zero, so PCI Master won't ever do any
accesses and PCI Target never drives FRAME or
IRDY.

I'm puzzled why this doesn't work for you!
I have only one idea left (it's a long shot though :)):
Can it be, that device isn't shown at boot-up because
BIOS doesn't recognize the vendor ID? Can you change
it to the Altera's core one and try that?
The only other course of action I can recommend from
here on is simulation - just read vendor/device ID and
configure BAR's. Then if this works, work through
gate level and timing simulations - if it's not board
problem, the thing should break at some point.

Is there anyone on the list using the core in Altera to
help us out? I know that at least a few people have used the core
succesfully on Altera.

Best regards,
Miha Dolenc

----- Original Message ----- 
From: "Jeremy Hammer" <jeremyh@c...>
To: "Discussion list about free, open source PCI IP core"
<pci@o...>
Sent: Friday, August 03, 2007 7:56 PM
Subject: Re: [pci] pci_bridge32 on an Altera Cyclone II

> Hi,
>
> I am going through the compile output and these lines are particularly
> concerning to me.
>
> Info: Pin pci_framen has a permanently disabled output enable
> Info: Pin pci_irdyn has a permanently disabled output enable
>
> Info: Pin pci_framen has VCC driving its datain port
>
> I am following the signals to their origin and they seem to be fine,
> although it gets difficult to tell when you go in deep.
>
> Also, I put the PCI I/O assignments on and it didn't help. And yes I found
> the correct way to assign the PCI I/O assignments to the pins.
>
> What are your thoughts on the three "Info" lines from my compile?
>
> Thanks!
> -Jeremy
> _______________________________________________
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