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Hi,

Hi Miha,
I have put a new top level at http://www.cetoncorp.com/pci_wb_test.v
There is now a define at the top of the file called USE_WB which 
switches between pci_bridge32 and the altera PCI core.  If I leave the 
define commented out (using altera's pci core) it works fine, if I leave 
it in (using pci_bridge32) it does not work.  I did this to verify the 
IO signals are correct on the project.

In this file there are some extra signals (pme and m66en) which are for 
my board.  Also, idsel is ad[24] on my board so it is commented out in 
the input listing.  Again, this works with altera's so I know the 
project and these signals are correct.

I changed bufif0 to en ? 1'bz : data and it did not change anything.

I'm not sure what to do now.  Do you happen to have a very simple top 
level you know works in other systems I could try?  I saw one in the 
source but it had tons of rams and was specific to Xilinx.

Thanks for your help,
-Jeremy

Miha Dolenc wrote:
> Hi,
> 
> your assumptions regarding PCI BARs' configuration are correct.
> I've taken a look at the top level, it seems allright.
> I suggest changing "bufif0" instances with generic code (you know en ? 
> 1'bz : data).
> Have you selected PCI I/O standard for your top level signals?
> 
> Best regards,
> Miha Dolenc
> 
> ----- Original Message ----- From: "Jeremy Hammer" <jeremyh@c...>
> To: <pci@o...>
> Sent: Monday, July 30, 2007 6:32 PM
> Subject: [pci] pci_bridge32 on an Altera Cyclone II
> 
> 
>> Hi,
>>
>> I am trying to get the pci_bridge32 to be recognized by my 
>> motherboard. I have used the Altera PCI IP Core on the board and it 
>> works fine so I know it is not a board issue.
>>
>> When using pci_bridge32 it does not show up in the "PCI devices list" 
>> on boot up.
>>
>> You can see my top level at http://www.cetoncorp.com/pci_wb_test.v
>>
>> I have stubbed out the wb interfaces, I am never doing an interrupt 
>> and use bufif0 for tri-stating.
>>
>> If someone could take a look and see if something pops out at them I 
>> would greatly appreciate it!
>>
>> Also, I am using the default (currently in CVS) pci_user_constants.v
>>
>> One other thing. I need to make one 32k memory bar. The 
>> pci_user_constants are a little confusing to me.  Bars on the PCI side 
>> are images correct?
>>
>> So if I comment out PCI_IMAGE2-5 I should have PCI_IMAGE0 (config 
>> space) and PCI_IMAGE1 (the first bar) created for me right?
>>
>> To make it a memory space instead of IO I need to make PCI_BA1_MEM_IO 
>> 1'b0.
>>
>> And to make it 32k I need to make PCI_NUM_OF_DEC_ADDR_LINES 17.
>>
>> I have ADDR_TRAN_IMPL commented out right now so the address 
>> translation stuff shouldn't matter I think.
>>
>> I just want to make sure I am understanding this correctly since I 
>> can't seem to get it working to check my assumptions.
>>
>> Thanks!
>> -Jeremy
>> _______________________________________________
>> http://www.opencores.org/mailman/listinfo/pci 
> 
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