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Message
From: Mark McDougall<markm@v...>
Date: Tue Mar 27 02:44:50 CEST 2007
Subject: [pci] PCI Target
Mau Liste wrote:> I prefer to use the PCI Target, because it looks more similar to what I
> need, and because it is written in VHDL which I am more confident with.
> My concern is that the PCI Target is marked as Beta.
>From memory the target has several limitations:
* only 1 BAR
* 16-bit wishbone interface
* no burst transfers
> On the other side, is it possible to tear down the full PCI Bridge with
> only the functionality I need (some ifdefs, maybe)?
The optimiser does a reasonable job without having to tear anything out.
For a previous design we used bus mastering and the core was 2848 LEs on
a Cyclone II platform. In a current design we're only using it as a
target, and it's 1804 LEs (same silicon). We didn't bother disconnecting
anything at all (other than slave-side wishbone buses of course) because
atm we aren't short of resources.
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
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