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On Mon, Mar 26, 2007 at 03:08:20PM +0200, Mau Liste wrote:

Thanks for your reply.
I tried that. The problem is that you need to do the same on the PCI
side, and it is not so clear to me how to do it.
As an example, take the pci_frame signal. On a target only, this is an
input, but the full bridge have three signals instead:
    pci_frame_i : in std_logic;
    pci_frame_o : out std_logic;
    pci_frame_oe_o : out std_logic;
It looks like it is possible to connect only the pci_frame_i leaving the
others disconnected. More difficult is the pci_par that still needs to
be a full io.
Anyway, I tried to do that also on the pci side, and I get a lot of
warning about removed logic ... good.
What I don't know is if the remaining logic is still working :(
I tried a few simulations and seems nothing is working.
So the question is: has anybody tried that?

Thank you.
Mau.

Andreas Ehliar wrote:
> On Mon, Mar 26, 2007 at 03:08:20PM +0200, Mau Liste wrote:
>> On the other side, is it possible to tear down the full PCI Bridge with
>> only the functionality I need (some ifdefs, maybe)?
> 
> A simple test would be to just input all zeros on the wishbone master
> side and see how much of the design that is optimized away by the
> synthesizer...
> 
> /Andreas
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