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Message
From: Gilles Primault<gilles.primault@h...>
Date: Wed Mar 7 10:19:44 CET 2007
Subject: [pci] Configuration Problem resolved!
Hi everybody
I found the solution to my configuration problem.
I used Altera RAM blocks with post-synch registers. These registers add
a one-clock period delay at fifos outputs. This make the command signals
coming too late at the pci_master_if entry.
Many thanks for the work done for this IP.
Bye
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