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Message
From: Jeff Carr<basilarchia@g...>
Date: Wed Feb 7 06:53:05 CET 2007
Subject: [pci] upload of port of the raggedstone pci core
I've been converting the port of the raggedstone pci core from vhdl to
verilog. Some people emailed me about it so I finally got a chance to
upload it today. It's not finished as I'm stuck converting a vhdl
state machine to verilog. Still, it's there up not for what it's worth.
This port was done by Manuel Bessler:
http://projects.varxec.net/raggedstone1
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