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    Navigation: All forums > Pci > Message List > Message Post

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    From: Robert Lluís<rlluis@p...>
    Date: Mon Jul 3 07:52:28 CEST 2006
    Subject: [pci] Issues with the PCI core
    Top
    Hello,

    I used to experience the performance problem reported below by Andreas
    Ehliar in this mailing-list.
    I have fixed this issue by following Ehliar's suggestion -see below. If
    someone is interested drop me an e-mail.

    Regards,
    Robert Lluis



    > The asynchronuous FIFO should be modified to include a high watermark
    > signal which is set to one if less than 32 words are available in the
    > FIFO. The state machine for the wishbone slave should be modified to
    > work in the following way:
    >
    > If a transaction is already under way, ignore the high watermark
    > signal. If a transaction has not started, only allow it to start if
    > the high watermark signal is zero.
    >



    > First, a performance problem:
    >
    > If we (via burst writes from the WB side to the PCI side) fill up the
    > asynchronuous fifos in the core the performance will go from high to
    > very low and never recover. The reason is that the asynchronuous
    > fifos do not deal with anything less than a complete burst
    > transaction. If the complete burst fits into the FIFO all is
    > well. However, if the burst does not fit into the fifo, the logic
    > around the fifo will end the burst transaction and start a new burst
    > transaction as soon as there is new space in the fifo. This new burst
    > will not be very long since there is very little space in the fifo at
    > this point.
    >
    > This means that as soon as the fifo is full we will not be able to
    > write a long burst into the fifo until it is relatively empty. Since
    > we will continue writing short bursts into the fifo, the PCI side will
    > only issue short bursts and therefore taking a very long time to drain
    > the fifo.
    >
    > An illustration of what this problem looks like is located at
    > http://www.da.isy.liu.se/~ehliar/opencores/pciburststuff.png
    > Source code for the testbench is at:
    > http://www.da.isy.liu.se/~ehliar/opencores/pciburststuff.tar.gz
    >
    > Perhaps this is the reason why some people claim that the core has
    > poor performance? How much work would it be to modify the core to be
    > able to merge burst transactions?
    >


     
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