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From: Ludwig Jaffe<jaffe@o...>
Date: Thu Feb 2 09:10:01 CET 2006
Subject: [pci] Re: Anyone have a Specification for PCI Express?
Chander Kavalipati wrote:
> LuJa,
>
> Does programming of the FPGA (or FPGAs) happens through a separate
> GPIO interface or through PCI? If understand it correctly there is a
> GPIO interface for this. Correct?
>
> What are the steps that one need to follow to reprogram the KAD? Can
> we dynamically reprogram the KAD with another design, without a
> reboot, with or without the assistance of special hardware?
>
> thanks,
> Chander.
>

Hi,

Programming happens "through pci" the reconfigurator fpga is accessible
via wishbone. The wishbone-Bus is accessible via the pci2wb-bridge that is
implemented in a sram based fpga.
Programming is as follows: Power-up, reset of pci. The reconfigurator
fpga looks if
a sd-card is plugged. if so, it reads the first sectors and knows which
data has to go where.
Then it programms the fpgas using the programming lines with the
contents that lies between the address-
pointers that are given in the first some bytes of the sd-card.
While programming it pulls reset on pci.
If no sdcard is present the fpga reads an onboard flash and programs the
bridge-fpga (fpga between pci and wishbone)
After programming it releases reset.
Now if we are a pci-peripheral the pc does its config-cycles and sets-up
pci-address ranges according to config space-data.
Now the pc boots. Having gone through the bootloader the patched
linux-kernel recognizes the pci2wb-bridge and reconf-driver is activated.

Reconfiguration is done by loading special kernel-modules that request
the reconf-driver to load a certain core on some fpga
(here there is some handshake about occupied and free fpgas)
The Reconfigurator is addressed by the reconf-driver as it lies in
PCI-Address-space, which is translated to WB-Address-Space by the
pci2wb-bridge
which acts like an embedded-bridge. As the wb-address of the
reconfigurator is fixed, the kernel-driver knows the offset from the
pci-address-room of the kad
and can access the registers of the reconfigurator via pci and the
bridge. To save on wires the bridge-fpga containing the
pci2Wishbone-bridge decodes
the address-space for the reconfigurator, so it needs only a few
address-lines and 32 data-lines.

So having the system up and running one can load and unload fpga code as
one likes (to prevent the bridge from beeing reconfigured -> crash it
has to be protected somehow e.g. one has to know a magic number) . This
allows for reconfigurable computing. If one wants to accelerate AES he loads
an aes-KAD-kernel-module containing an aes-core for a fpga. The
reconfigurator-driver will configure the desired fpga if empty or any
empty fpga (has to be configured in the driver).
The design of the KAD aims to be entirely field-upgradeable. Wait for
the spec because reprogramming the reconfigurator is not that easy.

So one does not need a reboot exept when one likes to play with
fpga-based cpus because a new cpu would require new configcycles. Maybe,
some magic bootstrapping may get along without reboot, but in
sd-card-mode the card is intended to preload the fpgas after reset
depending on the card-contents with the appropriate core. For
CPU-experiments.
RAM has to be plugged onto the KAD using the user-extension-connectors.
(Maybe, we use more than 64 pins, but this will be decided when
designing the board-layout, two pmc-connectors (64pins each) are nice to
have, one is a must).

Maybe you want to watch the recordings of my lectures held at 21c3 or
what-the-hack proving that my english is not the best :-)

21c3 recordings are here:
ftp://ftp.ccc.de/congress/2004/set/The Kernel Accelerator Device.mp4
ftp://ftp.ccc.de/congress/2004/set/The Kernel Accelerator Device.mp3
ftp://ftp.ccc.de/congress/2004/set/The Kernel Accelerator Device.pdf


Greetings


LuJa

>
> On 2/1/06, Ludwig Jaffe <jaffe@o...> wrote:
>
>> The KAD uses a reconfigurator (some means of better GPIO)
>> that talks to the programming-lines and jtag for debug of the FPGA. Here
>> a small flash-based-FPGA (actel)
>> or a cpld will do the job of maintaining a list, wich fpgas are
>> programmable, and which are occupied and
>> it will also do the talk to the fpgas in means of programming them.
>> As a special feature it is planned to read a mmc/sd-card so the
>> flash-fpga/cpld can programm all
>> the fpgas after reset. So it will be possible with an enhanced
>> pci2wb-bridge (needs to do config-cycles) to play around with
>> cpu-cores as the kad will then act as pic-mg cpu card (having normal
>> pci-peripherals plugget in a picmg-backplane) when the other fpgas are >> setup accordingly. >> >> To make a long story short: >> the kad is intended to be a universal development plattform. The Ideas >> and concepts are almost done. >> When I find time 1-2 Weeks I write a big spec about the kad. Schematic >> design will take place in gEDA >> for open-source political reasons. PCB-Layout is not figured out. As we >> can export Netlists, we might go >> with cadence allegro (a friend of mine has it in his company, and he >> would help me with the layout for some beer in exchange:- ) if the >> design is complicated, >> or stay with gnu pcb. In the allegro-scenario the layout will be >> post-documented in gnu-pcb making it free >> >> After thinking back and forward we decided to implement the wishbone bus >> >>> 108 lines as bussed wires on the board. >>> >> Here the electric specification of pci 3.3V shall be reused. Former >> Ideas with LVDS and quadpumping have been found to be >> not feasible because of impedance-maching problems in the bus. (We have >> a point2multipoint bus that should be as fast as possible. >> Unfortunately, the WB has so many signals (more than pci!). This means >> layout-effort, and problems with proper >> termination). After some discussion with friends, I think we use the pci >> way of thermination (clipping-diodes) which are >> part of the fpgas, because they claim to be pci-compliant. Because of >> long turn-around between transmtiter and reveiver >> one databus master2slave-send and slave2master-send should be used. Here >> we are not shure because of layout-effort. >> >> At the moment, we want to go with altera cyclone2 in bga484-packacke, >> because of the big wishbone, 64 User-IOs that are >> availlable on a PMC-Connector, and some sort of "transputerlinks" that >> interconnect fpgas which are next to eachother. Here >> the buswidth and the protocoll is not settled. Maybe, we ise the >> iso-standard for transputerlinks, maybe, we make the bus a little bit >> bigger.. >> These transputerlinks are point2point and properly terminated to give >> highest possible speed, as they are intended to be used asynchronous >> fast inter-fpga-communication will be possible. >> (Hagen is fiddling around with a altera cyclone2 versus xilinx-spartan3 >> migration-pinning, but this is only nice-to have, because we will loose >> IOs.) >> >> Regarding PCI-Express: Here the phillips-phy PX1011A and one not-used >> "reansputer-link" will be used. The "transputer-link" hat approx. 9 >> lines per direction. >> beeing a fpga at one edge it needs only 2 instead of 3 links. >> >> The Card will be universal. One PCI-edgeconnector at bottom left, one >> pci-express-edgeconnector at up-right. So one can rotate the card to >> plug it into pci-express (nice hack, isnt' it?) >> >> >> Wait for the spec. There will be more in it. >> >> >> I am happy to discuss it with you folks in some weeks, because we do not >> want to do many changes in schematics, or even worse in layout. >> >> >> Greetings >> >> >> LuJa >> >> >> >> Chander Kavalipati wrote: >> >>> Hi LuJa, >>> >>> This idea about KAD sounds interesting. I was also thinking on similar >>> lines. An open source design can really fuel more applications based >>> on it. >>> >>> Did you make any progress so far? I would like to take a look at your >>> board design. What FPGA device are you planning to use? This KAD >>> should have some knowledge of the PCI and an ability to load the >>> design into FPGA. How do you plan to achieve it? >>> >>> cheers, >>> Chandra. >>> >>> >>> >>> On 1/31/06, Ludwig Jaffe <jaffe@o...> wrote: >>> >>> >>>> Hi dave, >>>> >>>> it still works: >>>> >>>> >>>> >> http://web.archive.org/web/20040128025958/http://chemie.pedf.cuni.cz/eagle/documents/pci_express_10.pdf >> >>>> Have fun with it! >>>> >>>> lets join forces. I want to develop the kernel-accelerator-device < >>>> http://www.openhardware.de/digital/kad/ > which is a PCI-Card having >>>> reprogrammable FPGAs on it >>>> to accelerate the linux-kernel for tasks like AES, video transcoding. >>>> Additionally the KAD will be an universal development- >>>> plattform. So one can build an oscilloscope, Logic-Analyzer, >>>> pattern-generator, function-generator, software-definded Radio >>>> (Receiver, Transmitter), and even an incircuit emulator for some >>>> controllers. It depends only on cores which are to be written and >>>> Add-On-Modules that are to be designed. The KAD is as open as possible. >>>> >>>> The KAD will base on wishbone. So the PCI2WB-Bridge is essential. A >>>> PCI-Express2WB-Bridge would be great! >>>> Is your Design an addon for the PCI2WB-Bridge? If so, it would be great, >>>> Hagen (www.chipforge.org) and I would be pleased to support you. >>>> >>>> Greetings >>>> >>>> >>>> LuJa >>>> >>>> >>>> >>>> >>>> dave@l... wrote: >>>> >>>> >>>>> Hi Ludwig, >>>>> >>>>> The net police got in and broke the link before I could download it! >>>>> >>>>> Thanks anyway >>>>> >>>>> Dave >>>>> >>>>> ----- Original Message ----- >>>>> From: Ludwig Jaffe<jaffe@o...> >>>>> To: >>>>> Date: Wed Jan 25 17:24:26 CET 2006 >>>>> Subject: [pci] Anyone have a Specification for PCI Express? >>>>> >>>>> >>>>> >>>>> >>>>>> pkk at spth.de wrote: >>>>>> >>>>>> >>>>>> >>>>>>> On Wed, 25 Jan 2006 14:24:52 +0100 (CET) >>>>>>> dave at luscher.co.uk wrote: >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>>> I am interested in doing an add-in board for a PC using >>>>>>>> >>>>>>>> >>>>>>>> >>>>>> PCI Express. >>>>>> >>>>>> >>>>>> >>>>>>>> PCI-SIG won't let anyone have the specification without >>>>>>>> >>>>>>>> >>>>>>>> >>>>>> paying. Can >>>>>> >>>>>> >>>>>> >>>>>>>> anyone help, I need the mechanical, electrical and ideally >>>>>>>> >>>>>>>> >>>>>>>> >>>>>> the protocol. >>>>>> >>>>>> >>>>>> >>>>>>>> Given that Phillips and TI make the physical to xpipe (2.5 >>>>>>>> >>>>>>>> >>>>>>>> >>>>>> Gbit Serdes) >>>>>> >>>>>> >>>>>> >>>>>>>> then an open core for PCI Express is possible. Is anyone >>>>>>>> >>>>>>>> >>>>>>>> >>>>>> interested? >>>>>> >>>>>> >>>>>> >>>>>>> I don't have the specification, but the book "PCI Express >>>>>>> >>>>>>> >>>>>>> >>>>>> System Architecture" should contain most or all of the info >>>>>> needed. >>>>>> >>>>>> >>>>>> >>>>>>> I once saw a draft of the specification on the site of a >>>>>>> >>>>>>> >>>>>>> >>>>>> european university once, but I don't remeber the URL. >>>>>> >>>>>> >>>>>> >>>>>>> Philipp >>>>>>> _______________________________________________ >>>>>>> http://www.opencores.org/mailman/listinfo/pci >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>> Here you are: >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> >>>>> http://web.archive.org/web/*/http://chemie.pedf.cuni.cz/eagle/docum >>>>> ents/pci_express_10.pdf >>>>> >>>>> >>>>> >>>>>> The link works. >>>>>> LuJa >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> >>>>> _______________________________________________ >>>>> http://www.opencores.org/mailman/listinfo/pci >>>>> >>>>> >>>>> >>>>> >>>> >>> _______________________________________________ >>> http://www.opencores.org/mailman/listinfo/pci >>> >>> >>> >> _______________________________________________ >> http://www.opencores.org/mailman/listinfo/pci >> >> > _______________________________________________ > http://www.opencores.org/mailman/listinfo/pci > >

Reference	Author
[pci] Re: Anyone have a Specification for PCI Express?	Chander Kavalipati